Reference is made to FIG. 1 which illustrates a prior art buffer circuit 10 comprising a pair of series connected CMOS inverters 12. Each inverter 12 is formed of a p-channel MOSFET (pMOS) 14 having a source-drain path coupled in series with the source-drain path of an n-channel MOSFET (nMOS) 16. More particularly, the source terminal and transistor body (bulk or well) of the pMOS transistor 14 are coupled to a high supply node 18 and the source terminal and body (bulk or well) of the nMOS transistor 16 are coupled to a low supply node 20. The high and low supply nodes 18 and 20, respectively, receive high and low supply voltages associated with a supply voltage domain. For example, the high supply voltage, referred to as Vdd, may comprise 1.8 Volts and the low supply voltage, referred to as ground, may comprise 0 Volts. The gate terminals of the pMOS transistor 14 and nMOS transistor 16 are coupled together at an inverter input node 22. The drain terminals of the pMOS transistor 14 and nMOS transistor 16 are coupled together at an inverter output node 24. With the series connection of the CMOS inverters 12, the inverter output node 24 of a first one of the inverters is coupled to the inverter input node 22 of a second one of the inverters.
The operation of the inverters 12 is well known to those skilled in the art. In response to a logic high signal at the inverter input node 22, the pMOS transistor 14 is turned off and the nMOS transistor 16 is turned on. The inverter output node 24 is accordingly coupled to the low supply node 20 and the inverter outputs a logic low signal. Conversely, in response to a logic low signal at the inverter input node 22, the pMOS transistor 14 is turned on and the nMOS transistor 16 is turned off. The inverter output node 24 is accordingly coupled to the high supply node 18 and the inverter outputs a logic high signal. The back-to-back inversions provided by the series connected inverters 12 provide a signal buffering operation with the input signal IN and output signal OUT having a same logic state.
It is common for the supply range of the input signal IN to be the same as the supply range of the supply voltage domain for the circuit 10. In such scenarios, static leakage of the circuit 10 is well within specifications at all times because one of the pull up transistor or pull down transistor of each inverter will be completely turned off.
However, certain circumstances exist where the supply range of the input signal IN may be different from the supply range of the supply voltage domain for the circuit 10. A common situation is a buffering operation with respect to an input signal whose supply range is less than the supply range of the circuit 10. In such a scenario, there is a significant increase in static leakage because the logic high voltage of the input signal (at 1.2V, for example) is not sufficiently high enough to fully turn off the pMOS transistor 14 (referenced to Vdd=1.8V. for example).
To address the static leakage issue, a commonly used design solution is to reduce the strength of the pMOS transistor 14. This unfortunately has an adverse effect on the switching speed of the buffer circuit 10. Such a circuit would be suitable only for low speed applications. For high speed applications, another solution is needed.
There is accordingly a need in the art for a buffer circuit with reduced static current leakage which is suitable for high speed applications.